Executive Certification in ASIC Verification

BY
iHUB DivyaSampark via Maven Silicon

Empowers participants with hands-on skills essential for modern semiconductor verification careers.

Mode

Online

Duration

9 Months

Fees

₹ 200000

Quick Facts

particular details
Medium of instructions English
Mode of learning Self study, Virtual Classroom +1 more
Mode of Delivery Video and Text Based

Course overview

The Executive Certification in ASIC Verification course is a rigorous training program designed to equip participants with industry-standard skills in ASIC and SoC verification, combining academic excellence with practical application. Offered by iHUB DivyaSampark at IIT Roorkee in collaboration with Maven Silicon.This Executive Certification in ASIC Verification course blends theoretical foundations with hands-on labs and real-world case studies, making it ideal for engineers, designers, and professionals seeking to specialize in semiconductor verification or break into VLSI careers. Through this pathway, participants gain a deep understanding of verification methodologies, SystemVerilog, UVM, formal techniques, and tool-based automation workflows that are critical in today’s chip development ecosystem. 

Spanning a comprehensive curriculum delivered through online and live sessions, the certification also includes masterclasses by faculty from premier institutions and expert industry practitioners. Hands-on projects, 24×7 lab access, personalized mentoring, and guidance on verification workflows ensure that learners emerge from the course with readiness to contribute to advanced semiconductor projects. 

The highlights

  • 9 months duration
  • Exclusive 2-Day Campus Immersion Experience
  • Official Certification by iHUB DivyaSampark, IIT Roorkee
  • Comprehensive Placement Support
  • Expert faculties

Program offerings

  • Industry experts
  • Real world projects
  • Eda tool access
  • Placement assistance
  • Campus immersion

Course and certificate fees

Fees information
₹ 200,000
The fees for the Executive Certification in ASIC Verification course are: 

Fees components

Amount

Course fees

Rs. 2,00,000 + GST

certificate availability

Yes

Eligibility criteria

The participants must have a minimum of 60% throughout their academic record and hold a BE/BTech degree in EEE, ECE, TE, CSE, IT, or Instrumentation, or a ME/MTech/MS in Electronics/MSc Electronics from a recognized institution. The participants should have less than two years of work experience, with a maximum career gap of one year, and must have no standing backlogs at the time of application. To qualify for placement support, participants are required to secure a minimum of 70% in the Final Placement Test conducted by Maven Silicon. 

What you will learn

Knowledge of python Knowledge of linux Knowledge of digital tools Database knowledge

The participants will develop proficiency in core verification principles that bridge foundational understanding and industry practice. Starting with digital design fundamentals and ASIC verification philosophies, you will explore Advanced Verilog, coverage analysis, and sophisticated SystemVerilog constructs to build robust testbenches. Training emphasizes practical verification planning, coverage metrics, and creating reusable verification environments that mirror industry expectations.

The curriculum introduces Universal Verification Methodology (UVM), including factory constructs, sequences, environments, and verification components to automate complex test scenarios. The participants will also engage with formal verification techniques, understanding how to apply assertions and formal tools to ensure design correctness. This Executive Certification in ASIC Verification course teaches automation with Python and C languages to streamline regression workflows and write firmware test cases for SoC-level validation. Through labs, embedded projects, and debugging case studies, participants will finish the Executive Certification in ASIC Verification course ready to tackle verification challenges in real ASIC and SoC development cycles. 

The syllabus

Module I: Advanced Verilog and Code Coverage

  • Timescale System Task
  •  Generate Blocks
  •  Self-checking Testbench
  •  Named Events
  •  Verilog Stratified Event Queue
  •  Statement Coverage
  •  Branch Coverage
  •  Toggle Coverage
  •  Finite State Machine Coverage
  •  Hands-On La

Module II: ASIC Verification Methodology

  • Verification Essentials
  • DV concepts and flow
  • Testplan
  • Directed Vs Random Testcases
  • Constraint Random Cov

Module III: RISC-V Instruction Set Architecture

  • RISC-V processor overview
  •  RISC-V ISA overview
  •  RV32I – R Type Instruction
  •  RV32I – I Type Instruction
  •  RV32I – S & B Type Instructions
  •  RV-32I – J & U Type Instructions
  •  RV32I – Assembly programs and
  •  Summary

Module IV: SystemVerilog Assertions (SVA)

  • Different types of Operating System
  • Design Features & layers
  • Basic Linux commands
  • Advanced commands
  • Utilities
  • Vi editor
  • Networking in Linux
  • Hands-On Labs

Module V: SystemVerilog HVL

  • Types of Version Control System
  • Git - Basic Workflow
  • Git - Various commands
  • Git - Branching & Merging
  • Git - Configuration
  • Hands-On Labs

Module VI: Universal Verification Methodology (UVM)

  • SystemVerilog Datatypes
  • SystemVerilog Memories
  • SystemVerilog Tasks & Functions
  • Object Oriented Programming - Basic
  • Object Oriented Programming - Advanced
  • SV Randomization
  • SV Threads, Mailbox and Semaphores
  • SV Virtual Interfaces
  • Functional Coverage
  • Case Studies
  • Hands-On Labs

Module VII: Formal Verification

  • Different types of assertions
  • Sequences
  • Different Operators & Sequence
  • Compositions
  • Definition of reusable sequences and properties
  • Connecting Assertions to DUT
  • SVA Coverage and Control Tasks
  • Hands-On Labs

Module VIII: Git Version Control System

  • Emergence of Formal Verification
  • Formal Verification Algorithms
  • Formal Property Verification
  • Formal Equivalence Checking
  • Types of Equivalence Checking
  • Hands-On Labs

Module IX: Linux Operating System

  • UVM Overview
  • UVM TB Architecture and Base Class Hierarchy
  • UVM Factory
  • Stimulus Modelling & Testbench Overview
  • UVM Phases and Reporting Mechanism
  • TLM Ports and Configuration
  • Creation of UVM TB Components
  • UVM Sequences
  • Virtual Sequences & Virtual Sequencers
  • UVM Events & Callbacks
  • Creating Scoreboard in UVM
  • Hands-On Labs

Module X: Gate Level Simulation (GLS)

  • GLS Timing Verification
  • GLS TB Setup and Environment
  • SDF Annotation
  • GLS Overhead
  • Improving GLS Performance
  • GLS Simulation Debugging
  • GLS Regression and Verification
  • Signoff
  • Case Study

Module XI: Low Power Verification

  • Necessity of Low Power
  • Unified Power Format [ UPF ]
  • Modeling Power Intent in UPF
  • Static Low Power Verification with UPF
  • Dynamic Low Power verification with UPF
  • Advanced UPF-Based Verification
  • Hands-On Labs

Module XII: Portable Stimulus Standard (PSS)

  • PSS Basics
  • PSS Constructs
  • Test Scenario Modeling
  • Coverage in PSS
  • Integration with Verification
  • Methodologies
  • Advanced PSS Concepts
  • Case Study

Module XIII: SoC Verification

  • C Programming
  • SoC Verification Methodology
  • Case Study

Module XIV: Generative AI for VLSI

  • Introduction to Gen AI
  • Large Language Models
  • Prompt Engineering
  • Model Fine Tuning and Domain-based
  • models for VLSI
  • Gen AI for VLSI
  • ML for EDA

Module XV: Python for DV Automation

  • Python Programming Basics
  • Python Fundamentals for DV
  • Python for Regression Testing
  • Log Parsing and Report Generation
  •  Case Study

Module XVI: Business Communication

  • Transition from College to Corporate
  • Interpersonal Skills and
  • Presentation Skills
  • Email Etiquette
  • Resume Writing
  • Mock Interviews: Technical/HR
  • Interview Skills: Group Discussion
  • and HR Round Preparation

Module XVII: Capstone Project

Admission details

  • Visit the official course URL : https://www.maven-silicon.com/ihub-roorkee-iit-certification-course-asic-verification/
  • Submit the application form
  • Then take an interview.

How it helps

Earning the certification validates participants' expertise in one of the most sought-after areas of semiconductor design. This certification enhances participant’s employability as a verification engineer, demonstrating proficiency in verification methodologies, advanced testbench creation, and automation techniques. Certified professionals are better positioned for roles in chip design houses, SoC verification teams, and R&D labs, often commanding stronger compensation and project responsibilities.

FAQs

What is the duration of the Executive Certification in ASIC Verification course?

The duration of this Executive Certification in ASIC Verification course is 9 months.

Is this certification recognized in the semiconductor industry?

Yes, it is certified by iHUB DivyaSampark, IIT Roorkee, and designed with industry relevance.

Can fresh graduates apply?

Yes, participants with relevant engineering degrees may apply. Work experience enhances prospects but is not compulsory.

What tools are used during the Executive Certification in ASIC Verification course?

Participants gain access to industry-standard EDA tools and labs for hands-on verification practice.

Is placement assistance guaranteed?

Placement support is provided, but outcomes depend on individual performance and market conditions.

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