Designed for engineers, professionals and graduates wanting to specialize in modern ASIC physical design flows.
Inclusive of GST
The Executive Certification in Physical Design and Signoff course is a meticulously crafted professional training program delivered by iHUB DivyaSampark, IIT Roorkee in collaboration with Maven Silicon, a reputed VLSI training and workforce development organization. Designed for engineers, professionals and graduates wanting to specialize in modern ASIC physical design flows.The Executive Certification in Physical Design and Signoff course combines academic rigor with practical exposure through structured labs, real-world projects, and masterclasses by top faculty and industry experts.
Over a 9 month duration, participants will gain foundational understanding of VLSI systems, digital logic, Verilog HDL design, CMOS fundamentals, and advanced ASIC Physical Design techniques such as floorplanning, placement, clock tree synthesis, routing, and timing closure. The Executive Certification in Physical Design and Signoff course culminates in preparing participants to manage the full ASIC flow from RTL to GDSII with real-tool experience and verification checks needed for successful tape-outs.
The fees for the Executive Certification in Physical Design and Signoff course is :
Fees components
Amount
Course fees
Rs. 2,00,000 + GST
Yes
iHUB DivyaSampark
The target audience for this includes:
Computer Hardware Engineer
The participants must have secured a minimum of 60% throughout their academic record and hold a BE/BTech degree in EEE, ECE, TE, CSE, IT, or Instrumentation, or a ME/MTech/MS in Electronics or MSc in Electronics from a recognized institution. The participants should have less than two years of work experience at the time of enrollment. To be eligible for placement support, participants must obtain a minimum score of 70% in the Final Placement Test conducted by Maven Silicon. Placement assistance will be provided for a maximum period of six months from the date of the first appearance for the Final Placement Test. Participants must have no more than one year of career gap and no standing backlogs during admission.
The participants will build strong fundamentals in VLSI architecture and digital logic before progressing into advanced aspects of ASIC physical design and physical verification. The Executive Certification in Physical Design and Signoff course covers everything from system-level overview of semiconductor design to hands-on hardware description using Verilog HDL, equipping participants with essential skills to translate design intent into manufacturable layouts. They will explore number systems, FSMs, memory design, and logic fundamentals that set the stage for complex RTL exercises and practical lab work.
The Executive Certification in Physical Design and Signoff course then drives into the heart of physical design learning industry-standard flows for placement, clock tree synthesis (CTS), routing, static timing analysis (STA), and power/timing optimization. Participants also gain proficiency in handling design rule checks (DRC), layout-versus-schematic (LVS) verification, and advanced challenges such as low-power optimization with UPF integration and signal integrity analyses. Combined with scripting skills and version control, this Executive Certification in Physical Design and Signoff course ensures participants are industry-ready to execute complex ASIC projects end-to-end.
Number Systems
Logic Gates
Designing Combinational Logic Circuits
Latches, Flipflops and Flipflop
Conversions
Registers & Counters
Frequency Dividers
Finite State Machines
Mealy & Moore FSMs
Sequential circuits using Finite
State Machines
Memories and Programmable
Logic Devices.
Asynchronous Sequential Circuits
Libraries and PDK's
Syntesis
Placement Process
Different Tasks in Placement
Goals of Placement
Pre-placement
Timing Optimization Techniques
Qualifying placement
Hands-On Labs
Earning this Certification empowers participants with an industry-recognized credential from IIT Roorkee, signaling their expertise and credibility in the semiconductor field. Participants gain deep knowledge of ASIC physical design flows and acquire hands-on experience with real-world EDA toolchains, preparing them for complex design and verification challenges. The certification significantly enhances employability for a variety of semiconductor and VLSI job roles while providing access to dedicated placement support services. The participants graduate with a strong portfolio built through extensive lab sessions and practical project work, showcasing their applied skills to prospective employers.
The Executive Certification in Physical Design and Signoff course runs for 9 months with online classes and practical labs.
Yes, 100% placement assistance is provided to eligible learners.
The participants will work with industry EDA tools for synthesis, place & route, STA, and physical verification.
Roles include Physical Design Engineer, ASIC Design Engineer, VLSI Design Engineer, among others.
No mandatory experience is needed, though a technical background is beneficial.
Brochure has been downloaded.
And never miss an important update
