- Design Metrics
- Fixed Function IC Technology
- Full Custom ASIC Technology
- Semi-Custom ASIC Technology
- HDL Role in System Design
- PLD Technology (PLA)
- PLD Technology (PAL)
- FPGA (Architecture)
- FPGA (Logic Implementation Examples)
- Challenge Your Self - 1
Online
₹ 1,299
Quick facts
particular | details | |
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Medium of instructions
English
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Mode of learning
Self study
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Mode of Delivery
Video and Text Based
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Course overview
Verilog is a text-based hardware description language used to describe electronic systems and circuits. Verilog is a language used in electronic design that could be used for system automation, timing analysis, testing procedure, and verification through simulations. Dr. Yogesh Misra, a professor at the GMR Institute of Technology in India, developed the System Design using Verilog online certification, which is provided by Udemy.
System Design using Verilog online course is designed for candidates who are interested in writing and simulating Verilog codes for digital circuits like combinational and sequential circuits. There are 29 hours of learning materials and downloadable study material for System Design using Verilog online classes that cover topics including dataflow modeling, behavioral modeling, structural modeling, Xilinx, blocking statements, non-blocking statements, the design matrix, test bench, and more.
The highlights
- Certificate of completion
- Self-paced course
- 29 hours of pre-recorded video content
- 1 downloadable resource
Program offerings
- Online course
- Learning resources. 30-day money-back guarantee
- Unlimited access
- Accessible on mobile devices and tv
Course and certificate fees
Fees information
certificate availability
certificate providing authority
What you will learn
After completing the System Design using Verilog certification course, candidates will gain a hands-on understanding of the fundamentals of Verilog programming for system design. Candidates will analyze the methods and procedures used in designing digital circuits such as sequential and combinational circuits. Candidates will gain knowledge of tactics related to IC technology, ASIC technology, PLD technology, behavioral modeling, structural modeling, and dataflow modeling. Candidates will also learn about test benches, blocking statements, and non-blocking statements.
Who it is for
The syllabus
IC Design Technology
Introduction to Verilog and Xilinx Software
- Introduction to Verilog
- Level of Abstraction
- Introduction to Xilinx Software
- Data Types (Net Types)
- Data Types (Register Types)
- Operator (Bitwise operators)
- Operator (Logical & Reduction)
- Operator (Arithmetic, Relational & Shift)
- Operator (Concatenation, Conditional & Replication)
- Challenge Your Self – 2
Introduction to different level of modeling
- Introduction to Structure Level Modeling
- Introduction to Behavioral Level Modeling
- Introduction to Dataflow Level Modeling
Testbench
- Test Bench-(Part I)
- Test Bench -(Part II)
- Test Bench-(Part III)
Structure Modeling
- Structure Modeling (2 to 1 Multiplexer)
- Structure Modeling (2 to 4 Decoder)
- Structure Modeling (3-Bit Adder) Part - I
- Structure Modeling (3-Bit Adder) Part - II
Behavioral Modeling
- Procedural Statements
- Sequential Statements (if-else) Part-I
- Sequential Statements (if-else) Part-II
- Sequential Statements (if-else) Part-III
- 2 to 4 Decoder using if-else Statement
- Comparator using “if-else” Statement
- Software demonstration of Comparator
- 2 to 1 Multiplexer using “case” Statement
- 4 to 1 Multiplexer using “case” Statement
- 2 to 4 Decoder using “case” Statement
- 1 Bit Comparator using “case” Statement
- BCD to 7 Segment Decoder using “case” Statement
- Sequential Statements - (loop)
Behavioral Model - Sequential Circuits
- Verilog code of D Flip Flop
- Verilog code of JK Flip Flop
- Verilog code of T Flip Flop
- Verilog code of 3 Bit Counter
- Parallel In Parallel Out Register
- Serial In Parallel Out Register
- Serial In Serial Out Register
Multiple Always Block
- Multiple always block - (Example)
- Multiple always block – (D Flip Flop)
- Multiple always block - (2 to 4 Decoder)
Blocking and Non-blocking Statements
- Blocking Statement
- Non-Blocking Statement
Few Examples of Combinational Circuits
- Verilog Model of Full Subtractor
- Binary to Gray Converter
- Gray to Binary Converter
- Verilog Code of 1 to 2 Demultiplexer
- Priority Encoder
Switch Level Modeling
- “cmos” Switch (Part I)
- “cmos” Switch (Part II)
- “cmos” Switch (Part III)
- “cmos” Switch (Part IV)
Instructors
Dr Yogesh Misra
Professor
GMRIT Rajam
B.E /B.Tech, M.E /M.Tech., Ph.D