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Quick Facts

Medium Of Instructions	Mode Of Learning	Mode Of Delivery
English	Self Study	Video and Text Based

Course Overview

The field of electronics has constantly been evolving and has witnessed morphological changes with the latest technologies. After the integrated circuit was invented, a new trend in the field of microelectronics set in. It leads to the miniaturisation of a lot of components like computers, mobiles, and laptops. The Advanced Certificate Program in VLSI System Design by MS Ramaiah University of Applied Sciences, Bangalore is a course that highlights and demonstrates the use of VLSI system design in integrated circuits.

The Advanced Certificate Program in VLSI System Design certification syllabus will guide learners through practical and theoretical concepts to undertake various roles in IC designing.

The Highlights

12 weeks of intensive learning
Blended mode of learning
Certificate of completion by MS Ramaiah University of Applied Sciences, Bangalore

Programme Offerings

Books
Study notes
Modules
labs
Projects
assignments

Courses and Certificate Fees

Certificate Availability	Certificate Providing Authority
yes	MSRUAS Bangalore

The fees may be paid in cash/DD at the University, The DDs must be drawn in favour of "M. S. Ramaiah University of Applied Sciences payable at Bangalore"

Advanced Certificate Program in VLSI System Design Fee Structure

Fee	Amount in INR
Registration Fee	Rs.2,000
Tuition Fee	Rs.27,000
Total Fee	Rs.29,000

Eligibility Criteria

Education

Advanced Certificate Program in VLSI System Design Certification Course can be pursued by graduates or postgraduates in Electrical & Electronics Engineering, Telecommunication Engineering, or Electronics & Communication engineering.

What you will learn

Knowledge of electronics

The Advanced Certificate Program in VLSI System Design certification course will accentuate the learning of course participants by providing valuable insights in the following ways-

The course has been crafted to boost the skills of learners so that they can learn to apply modern design principles in solving product design problems
Through lab work, candidates will be able to demonstrate modelling for application in developing design solutions
The Advanced Certificate Program in VLSI System Design Training will put the creative thinking ability of candidates to work and implore them to ideate innovative product design solutions
Through this course, learners will stay updated with the applications and recent developments in CAD technology
Students will learn to use cadence software proficiently

Who it is for

The Advanced Certificate Program in VLSI System Design is a full-fledged learning programme on VLSI system design that will aid the following candidates-

People having a graduate or postgraduate degree in Electronics & Communication engineering seeking a job opportunity as an electronics engineer
Graduates and postgraduates in Electrical & Electronics engineering willing to work in the circuit integration sector
Graduates and postgraduates in Telecommunication Engineering working on creating complex semiconductor technologies

The Syllabus

Advanced digital designs

Need for reconfigurable systems, Importance of reconfigurable systems in VLSI design
DSP processors vs. FPGAs, review of PLA, PAL, PLDs, CLB, ROM, PROM
Introduction to advanced digital designs (multipliers, adders, FSM’s, etc...)
Application for reconfigurable systems, need of FPGAs in DSP applications

HDL coding for synthesis

Developing linear testbench
Functions and tasks, UDPs, synthesizable and non-synthesizable constructs
Rules for combinational and sequential circuit’s synthesis (blocking, non-blocking)
Introduction to synthesis (operator, always, initial blocks, inter and intra assignment delays)
Introduction to RTL coding
Different levels of modelling (structural, behavioural, dataflow)

FPGA architectures

Distributed RAM, shift registers, digital clock managers
XILINX FPGA architectures, anti-fuse and SRAMS, logic elements and look-up tables, dedicated multipliers, reconfigurability
Spartan III, Artix-7 and Virtex architectures

FPGA implementation

Post map and post-P&R simulation, UCF constraints
Configuring FPGAs, FSM extraction
FPGA programming, translate, map, floorplan, place and route
Reading and analyzing reports-post synthesis, post map simulation, post-P&R simulation

Constraints

Maximum skew calculations with examples, period constraints
Timing analysis, slack calculation, data loss due to large skew
Area and power constraints

FPGA debugging

Protocols on FPGA & high-speed SERDES
Introduction and usage of IP cores
Introduction to FPGA debugging, debugging using chip scope and logic analyzers
Distributed arithmetic, the realization of FIR filter using MAC in FPGA

Verilog programming on structural modelling
Basic programming in Verilog
Verilog programming on dataflow modelling
Assigning UCF and advanced constraints
Dumping program on FPGA kit
Verilog programming on looping statements
Using IP cores
Verilog programming on conditional statements
Verilog programming on behavioural modelling
Debugging on FPGA using chip scope pro
Using DCM in FPGA
Verilog programming on test benches

Introduction to semi-custom design flow & standard cell libraries

Semi custom-oriented HDL coding
Introduction to semi-custom ASIC design flow, challenges and opportunities
Operating conditions, wire-load models, timing models, timing arcs, kinds of standard cells
Overview of industry-standard tools
Different kinds of libraries and their relevance
Setting the path for library and setup files

Static timing analysis

Timing exceptions, false path and multi-cycle path
Terminologies in timing analysis, various kinds of timing paths
The necessity of STA, advanced timing analysis
Properties of the clock, clock skew, solving complex timing problems

Synthesis and constraints

Low power techniques and constraints for Multi-VDD, multi VTH and optimization
Point-point exceptions, chip-level constraints
Design rule constraints, timing and power constraints

VLSI testing

Design for testability (DFT) design rule check boundary scanning
Need for testing and introduction to testing
Basic of testing like fault defect error stuck at faults

Generating netlist of the synthesized design
Understanding Verilog coding for synthesis
Setting up a library for synthesis
Generating DFT inserted netlist
Applying constraints on the design using CAD tool
Performing testing of the design using a testing compiler CAD tool
Performing synthesis on the design using synthesis compiler CAD tool
Performing timing constraints on the design using timing compiler CAD tool

Floor plan and power planning

TDF/IO constraint files, defining best aspect ratio, core utilization, chip utilization, flat & hierarchical design flow
Power management, core, and IO level power estimation
IC design flow data preparation process and set of libraries technology file, TLU+ resistance-capacitance timing models, LEF file setting of Milky way
Estimating power budget for flattened and hierarchical designs, placement of power mesh and power pads based on IR and EM-based criteria

Placement and optimization

High fan-out net synthesis, placement optimization tasks, power optimization, area recovery
Timing drove and timing the congestion, detaching scan chains, location constraints
Introduction to placement, standard cell, and macro/DEF placement

Clock tree synthesis

Local and useful skew analysis and optimization methodologies
Introduction and Algorithms for CTS
Path length and its delay models for skew analysis buffer insertion
Clock distribution network

Chip finishing

Design signoff, data preparation flow for power sign off
Performing design rule checking and connectivity verification
Crosstalk prevention, analysis and fixing
Checking physical and logical connectivity power information, preparing data for rail analysis based on IR and EM criteria

Importing SDC file for checking to time
Performing routing using CAD tools
Generating floor plan for the design using CAD tools
Performing CTS using CAD tools
Generating GDSII
Performing placement using CAD tools
To set up the library
To import the netlist for a physical design using CAD tools

MOS transistor theory

Structure and operation of MOS transistors
NMOS and PMOS transistor layout and design rules in nanometer technology
Analysis of current-voltage characteristics and biasing of MOS transistors

CMOS inverter design

CMOS inverter and its operation design of CMOS inverter
Optimization of CMOS inverter design for noise margin, speed, power, and timing
Modelling of CMOS inverter
The layout of CMOS inverter in nanometer technology combinational and sequential CMOS Logic Circuits
Analysis of static and dynamic characteristics of CMOS inverter

Combinational and sequential CMOS logic circuits

Standard cell design, input circuit and output circuit design
Layout design optimization techniques
Types of sequential circuits design, analysis and optimization of timing metric and performances parameters of sequential circuits
Analysis of the performance parameters of combinational logic circuits
Design of combinational logic circuits using CMOS logic gates
Estimation of delay in combinational CMOS circuits using logical effort

Memory design

Design of SRAM memory
SRAM and DRAM memory, SRAM and DRAM memory architectures
Design of SRAM peripheral circuitries-read/write circuitry, bit line recharge circuitry, and row and column/mux decoders

Low power CMOS circuit design

Simulation analysis of power dissipation in CMOS based circuits
Low power CMOS circuit design techniques from the device level to system level
Power dissipation in CMOS circuits: Static and dynamic power dissipation

Reliability issues

Reliability and DFM issues in nanometer technology IC design
Electromigration and its reduction techniques
Crosstalk and its effects on IC design
IR drop, Latch-up problem and latch-up prevention

Analysis of MOS Transistors
Layout design of MOS transistor and a CMOS inverter
Analysis of CMOS inverter static characteristic
Analysis of sequential logic circuits
Combinational circuit optimized layout design
Analysis of combinational logic circuits
Sequential circuit layout design
Sequential circuit optimized layout design
Combinational circuit layout design
Analysis of CMOS inverter dynamic characteristic

MSRUAS Bangalore Frequently Asked Questions (FAQ's)

1: How many hours do learners need to invest in lab sessions?

The Advanced Certificate Program in VLSI System Design Training shall comprise 70 hours of lab sessions for each module.

2: What are the hardware requirements for the Advanced Certificate Program in VLSI System Design Certification?

Candidates would require the following hardware-

Xilinx hardware kit(Virtex-2p, Virtex-5)
Artix-7
Altera
Cyclone
Cadence
Modelsim

3: Which books are recommended for the second module?

Candidates may refer to the following books-

Ban P. Wong, Anurag Mittal, Greg W. Starr, Franz Zach, Victor Moroz and Andrew Kahng.(2008) Nano-CMOS Design for Manufacturability, Wiley-Interscience
Sung Kyu Lim. (2008) Practical Problems in VLSI Physical Design Automation, Springer
Himanshu Bhatnagar. (2002) Advanced ASIC Chip Synthesis, Kluwer Academic Publishers
PranKurup. (2003)Logic Synthesis using Synopsys, 2nd edition, Kluwer Academic Publishers

4: How can students access the study material in the Advanced Certificate Program in VLSI System Design Certification?

Notes shall be shared with course participants in the PPT format after enrolment.