Certificate
VLSI chip is a modern and complex chip that is often called a remarkable beast. It packs a billion transistors, logic gates employed in millions to compute and control, huge memory blocks, a third party worked, pre-designed functions that come in blocks (IP blocks or Intellectual Property blocks) embedded in the chip. How can you actually design this chip? The sequence of CAD tools that use abstract descriptions provided for the chip which are refined meticulously in steps to come up with a final design.
This course is a second part of the VLSI CAD course called the certification course on VLSI CAD Part II: Layout. The course focuses on the important tools that are used for designing and creating an ASIC (Application Specific Integrated Circuit) or an SoC design process (System of Chip). The main target of this course is to help candidates develop an understanding and better knowledge of the key geometrical and logical representations that make it feasible to map from the logic part to layout and particularly to route, place, to evaluate the perfect timing of the large logic networks.
The VLSI CAD Part II: Layout certificate programme goal is that candidates should be able to utilize and understand the working of tools right at the basic level of its fundamental logic and algorithms and the supporting data structures. The Course is well-curated to include ASIC routing and placement, technology mapping, Analysis of timing involved, etc
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3
Weeks

Intermediate
₹ Free