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Quick Facts

Exam
GATE

Course Details

MODE

Full time

DURATION

24 Months

Master of Technology in VLSI Design and Embedded Systems is two years (4 Semester) full-time postgraduate engineering program offered by Siksha O' Anusandhan University, Bhubaneshwar.


Important dates

Exams and EventsDates
GATE
Exam Date (Mode - Online)
6 Feb'26 - 7 Feb'26
GATE
Exam Date (Mode - Online)
13 Feb'26 - 14 Feb'26
GATE
Result Date (Mode - Online)
18 Mar'26 - 18 Mar'26

Eligibility Criteria

Passed B.Tech. or equivalent in the relevant field. Obtained at least 60% marks (50% in case of candidate belongs to reserved category) in the qualifying Examination or passed M.Sc. (Electronics)  and 50% marks (45% marks in case of candidate belongs to SC / ST / OBC category) at 10+2 or equivalent examination. 


Admission Details

Admission into M.Tech. programmes will be done on the basis of performance in SAAT or valid GATE score.

Applications for Admissions are open.

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