- Introduction and Acknowledgements
- Need for characterization
Online
₹ 700 3,499
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Medium of instructions
English
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Mode of learning
Self study
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Mode of Delivery
Video and Text Based
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The syllabus
Introduction
Cell Design and Characterization Flows
- Inputs for Cell Design Flows
- Circuit design step
- Layout design step
- Typical characterization flow
General Timing Characterization Parameters
- Timing threshold definitions
- Propagation delay and transition time
- Output Current model and CCS table
- Output voltage waveform and introduction to tristate buffer
- Different transitions for tristate buffer
Timing Characterization Parameters for Registers
- Netlist connectivity for latch and flipflop
- Library setup time as a function of data and clock transition time
- True single phase clocked (TSPC) register for hold time evaluation
- Library setup time for TSPC register
- Hold time, recovery & removal time evaluation
Noise Characterization and Modelling
- Introduction to noise - Crosstalk glitch and delta delay
- Introduction to Channel Connected Components (CCC)
- ccsn_first_stage, ccsn_last_stage and VIVO model based dc_current
- Need of dc_current attribute
- Noise immunity curve, propagated_noise_high and propagated_noise_low
- stage_type attribute and need for tie_hi cells
- Miller cap, arc based ccs noise model and full noise library
Power Characterization and Modelling
- Static power - Subthreshold current and junction leakage current
- Static power - Tunnelling current
- Internal leakage power - leakage_current and leakage_power groups
- Internal leakage power - cell leakage power and tunneling current - gate leakage
- Dynamic power - Switching current
- Dynamic power - Short-circuit current
- Switching power and short-circuit power modelling
- Hidden power concept and modelling
Timing Modeling
- Groups and attributes
- Library group and its attributes
- Cell groups and combinational function pin groups
- Flip-flop modelling using 'ff' group
- Latch modelling using 'latch' group
- Introduction to 'statetable' and latch description using 'statetable' group
- Flip-flop modelling using 'statetable' group and introduction to 'driver model'
Conclusion
- Driver model, receiver model and conclusion
Instructors
Mr Kunal Ghosh
Director, instructors
Freelancer
M.E /M.Tech.