Executive Certification in VLSI Design for Testing

BY
iHUB DivyaSampark via Maven Silicon

Designed to equip professionals and students with the critical skills required for semiconductor design and testing.

Mode

Online

Duration

9 Months

Fees

₹ 200000

Important Dates

28 Feb, 2026

Course Commencement Date

Quick Facts

particular details
Medium of instructions English
Mode of learning Self study, Virtual Classroom +1 more

Course overview

The Executive Certification in VLSI Design for Testing course is offered by iHUB DivyaSampark, IIT Roorkee in collaboration with Maven Silicon. Spanning a comprehensive curriculum that combines live online classes, self-paced modules, and a 2-day campus immersion program. This Executive Certification in VLSI Design for Testing course ensures learners gain practical expertise in VLSI design, digital logic, CMOS fundamentals, synthesis, verification, and advanced DFT methodologies. Participants also get hands-on experience with industry-standard tools, Verilog HDL programming, and project-based learning to implement DFT on real SoC designs. 

iHUB DivyaSampark is a Section 8, not-for-profit Technology Innovation Hub at IIT Roorkee, established under the National Mission on Interdisciplinary Cyber-Physical Systems (NM-ICPS) by the Department of Science & Technology (DST), Government of India. The Executive Certification in VLSI Design for Testing course leverages the expertise of IIT faculties and industry professionals, focusing on the critical skill gap in India’s semiconductor ecosystem. With features like 24/7 lab access, mentorship, and masterclasses from eminent professors, learners are prepared for global semiconductor challenges, ensuring high-quality and reliable SoC designs for production.

The highlights

  • 9 months duration
  • Exclusive 2-Day Campus Immersion Experience
  • Official Certification by iHUB DivyaSampark, IIT Roorkee
  • Comprehensive Placement Support
  • Expert faculties

Program offerings

  • Industry experts
  • Real world projects
  • Eda tool access
  • Placement assistance
  • Campus immersion

Course and certificate fees

Fees information
₹ 200,000

The fees for the Executive Certification in VLSI Design for Testing course is : 

Fees components

Amount

Course fees

Rs. 2,00,000 + GST

certificate availability

Yes

certificate providing authority

iHUB DivyaSampark

Eligibility criteria

The participants should have completed their BE/BTech in EEE, ECE, TE, CSE, IT, or Instrumentation with a minimum of 60% throughout their academic career, or possess an ME, MTech, MS in Electronics, or MSc in Electronics. Work experience should be less than 2 years, and candidates must have no standing backlogs. The participants are required to achieve a minimum score of 70% in the Final Placement Test conducted by Maven Silicon. Placement assistance is provided for a maximum of six months following the first attempt at the Final Placement Test, and participants may have a career gap of no more than one year.

What you will learn

Knowledge of python Knowledge of digital tools Knowledge of linux

The participants will learn the entire VLSI design flow starting with digital logic, number systems, combinational and sequential circuits, FSMs, and memory design. The Executive Certification in VLSI Design for Testing course practical hardware design and verification using Verilog HDL, including coding styles, FSM design, and lab exercises. Participants also gain an in-depth understanding of CMOS fundamentals, synthesis, clock domain crossing, static timing analysis, equivalence checking, and physical design flow techniques like floor planning, placement, CTS, routing, layout compaction, and physical verification.

The DFT module trains participants in essential testing strategies such as scan insertion, ATPG, fault modeling, BIST, boundary scan, JTAG, and advanced low-power design testing. Automation with Python and Tcl scripting and version control with Git ensures participants are ready to apply industry-standard practices. Participants will be capable of executing a full-scale DFT implementation on an SoC, making them highly competent in semiconductor design and testing.

The syllabus

Module I: VLSI SoC Design

  • VLSI Technology Overview
  • Moore’s Law
  • IP, Subsystems, and Chips
  • SoC Architecture
  • SoC Design Process
  • System-Level Design - Hardware & Software
  • Semiconductor Industry Overview

Module II: SoC ASIC Design Flow

  • VLSI Design Flow
  • ASIC Vs FPGA

Module III: Advanced Digital Design

  • Number Systems
  • Logic Gates
  • Designing Combinational Logic Circuits
  • Latches, Flipflops and Flipflop
  • Conversions
  • Registers & Counters
  • Frequency Dividers
  • Finite State Machines
  • Mealy & Moore FSMs
  • Sequential circuits using Finite
  • State Machines
  • Memories and Programmable
  • Logic Devices.
  • Asynchronous Sequential Circuits

Module IV: RISC-V Instruction Set Architecture

  • RISC-V processor overview
  • RISC-V ISA overview
  • RV32I – R Type Instruction
  • RV32I – I Type Instruction
  • RV32I – S & B Type Instructions
  • RV-32I – J & U Type Instructions
  • RV32I – Assembly programs

Module V: Linux Operating System

  • Different types of Operating System
  •  Design Features & layers
  •  Basic Linux commands
  •  Advanced commands
  •  Utilities
  •  Vi editor
  •  Networking in Linux
  •  Hands-On Labs

Module VI: Verilog HDL

  • Introduction to EDA tools
  • Data Types
  • Verilog Operators
  • Advanced Verilog for Verification
  • Assignments
  • Synthesis Coding Styles
  • Finite State Machine
  • Hands-On Labs

Module VII: CMOS Fundamentals

  • MOSFET
  • CMOS Fabrication
  • CMOS Characteristics
  • CMOS Circuit Design
  • CMOS Transistor Sizing
  • Stick Diagrams and Layouts
  • Non-Ideal Characteristics
  • Hands-On Labs

Module VIII: Clock Domain Crossing

  • Introduction to Clock Domain
  • Crossing [ CDC ]
  • Different types of Synchronizers
  • CDC Analysis
  • Types of CDC errors
  • CDC Verification flow
  • Case Study

Module IX: Reset Domain Crossing

  • Introduction to Reset Domain
  • Crossing [ RDC ]
  • RDC Hazards and Issues
  • RDC Verification Techniques
  • Case Study

Module X: Static Timing Analysis [ STA ]

  • Types of Timing Analysis
  • STA in Design Flow
  • Different Timing Parameters
  • Techniques to improve Timing
  • Timing Analysis Procedures
  • Setup & Hold time violations
  • Eliminate Setup & Hold time violations
  • Hands-On Labs

Module XI: Perl Scripting

  • Datatypes
  • Operators
  • Conditional branches
  • Controlled loops
  • Subroutines
  • Special Variables
  • File Operations
  • Regular expressions
  • Processes
  • Modules & Packages
  • Assignments
  • Hands-On Labs

Module XII: Python

  • Datatypes and Operators
  • Functions and Loops
  • Python OOP
  • Exceptions
  • File IO Operations
  • Sequences and Methods
  • Hands-On Labs

Module XIII: GIT Version Control System [ VCS ]

  • Types of Version Control System
  • Git - Basic Workflow
  • Git - Various commands
  • Git - Branching & Merging
  • Git - Configuration
  • Hands-On Labs

Module XIV: Physical Design - Overview

  • Design Styles
  • Partitioning
  • Floorplanning
  • Placement
  • Clock Tree Synthesis [ CTS ]
  • Routing
  • Static Timing Analysis [ STA ]

Module XV: Design for Testing [ DFT ]

  • Importance of Testing
  • Outcome of Testing
  • ASIC Design Flow & Testing
  • Verification Vs Testing
  • Defect Vs Fault

Module XVI: Automatic Test Pattern Generator ( ATPG )

  • Types of Testing
  • Testing at different Abstraction Levels
  • Fault Modelling and Collapsing
  • ATPG Basics
  • Combinational ATPG
  • Tessent Shell Introduction
  • Fault Class
  • ATPG Basics
  • Hands-On Labs

Module XVII: Fault Models

  • Tessent Shell Usage
  • Additional Fault Models
  • Hands-On

Module XVIII: Scan Chain Insertion

  • Introduction to DFT
  • Scan Chain Insertion
  • Hands-On Labs

Module XIX: Test Compression

  • Test Compression Techniques
  • Hands-On

Module XX: Boundary Scan

  • Boundary Scan Architecture
  • Boundary Scan Instructions
  • Boundary Scan Applications
  • Hands-On Labs

Module XXI: Built In Self Test [ BIST ]

  • Introduction to BIST
  • Logic BIST [ LBIST ]
  • Memory BIST [ MB ]
  • Hands-On Labs

Module XXII: IJTAG

  • IJTAG Architecture
  • Hands-On Labs

Module XXIII: Low Power Design

  • Sources of Power Consumption
  • Different Techniques for Lowering
  • Power Consumption
  • Transistor resizing
  • Clock Gating
  • Sleep Transistors
  • Transistor reordering
  • Dynamic Voltage/Frequency Scaling
  • Isolation Cells and Level Shifters
  • Precomputation
  • Power Oriented Programming
  • Low Power Design Methodology (UPF)
  • Hands-On Labs

Module XXIV: DRC & Test Coverage

  • Design Rule Checks
  • Improving Test Coverage
  • Fault Diagnosis
  • Hands-On Labs

Module XXV: DFT for Analog Macros

  • DFT for Analog Macros
  • Hands-on Labs

Module XXVI: Gen AI for VLSI

  • Introduction to Gen AI
  • Large Language Models
  • Prompt Engineering
  • Model Fine Tuning and Domain-based
  • models for VLSI
  • Gen AI for VLSI
  • ML for EDA

Module XXVII: Business communication

  • Transition from College to Corporate
  • Interpersonal Skills and
  • Presentation Skills
  • Email Etiquette
  • Resume Writing
  • Mock Interviews: Technical/HR
  • Interview Skills: Group Discussion
  • and HR Round Preparation

Module XXVIII: Capstone Project

How it helps

Earning this certification validates expertise in VLSI Design for Testing, enhancing employability in the semiconductor sector. It provides recognition from IIT Roorkee and Maven Silicon, equipping participants with practical skills in SoC design, DFT methodologies, lab automation, and project execution. Certified professionals are prepared for leadership roles, complex design challenges, and global opportunities in chip design and testing.

FAQs

What is the duration of the Executive Certification in VLSI Design for Testing course?

The duration of this Executive Certification in VLSI Design for Testing course is 9 months.

Do I need prior VLSI experience?

Basic understanding of digital circuits is helpful but not mandatory.

What tools will I have access to?

24/7 lab access with EDA tools and Verilog HDL simulation platforms.

Is placement assistance provided?

Yes, the program offers 100% placement support with guidance for semiconductor careers.

Will I receive a certification after completion?

Yes, an official certificate from iHUB DivyaSampark, IIT Roorkee, is awarded after successful completion.

Are the classes online or offline?

The Executive Certification in VLSI Design for Testing course is primarily online, with optional in-person immersion at IIT Roorkee.

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