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M.Tech VLSI Design at YMCA Faridabad Offline Course
Approved by AICTE
24 Months
Full timeQuick Facts
Exam GATE | Seats 18 |
Course Details
MODE
Full timeDURATION
24 MonthsMaster of Technology (M.Tech) in VLSI Design is a full time two-year postgraduate degree course, and it is offered by the JC Bose University of Science and Technology, YMCA, Faridabad, or approved by AICTE.
Important dates
| Exams and Events | Dates |
|---|
GATE Application Date - Without late fee (Mode - Online) | 1 Sep'26 - 27 Sep'26 |
GATE Late Fee Application Date - With late fee (Mode - Online) | 4 Oct'26 - 4 Oct'26 |
GATE Application Correction Date (Mode - Online) | 13 Oct'26 - 20 Oct'26 |
GATE Choice of Exam City - City allotment (Mode - Online) | 3 Jan'27 - 3 Jan'27 |
GATE Exam Date (Mode - Online) | 5 Feb'27 - 6 Feb'27 |
GATE Exam Date (Mode - Online) | 12 Feb'27 - 13 Feb'27 |
GATE Exam Date (Mode - Online) | 19 Feb'27 - 20 Feb'27 |
GATE Result Date (Mode - Online) | 18 Mar'27 - 18 Mar'27 |
Eligibility Criteria
A candidate must have passed the B.E. / B.Tech or equivalent degree in Electronics & Communication / Electronics & Telecommunication Engg. / Electronics Engg. / Electrical & Electronics Engg. / applied Electronics & instrumentation Engg. / Electronics & Instrumentation & Control Engg. / Electrical Engg. / Instrumentation & Control Engg. / Instrumentation Engg. / Control Engg. / Biomedical Engg. / Mechatronics / or in relevant Branch or M.Sc. (Electronics) / M.Sc. (Physics) with specialization in Electronics) from a recognized University / Institution with at least 50% marks in aggregate (45% marks for SC / ST candidates of Haryana only). Result awaited (Qualifying Exam.) candidates can apply.
Admission Details
Admission shall be made firstly on the basis of valid GATE score merit. If the seats remain vacant, admission shall be made on the basis of merit of qualifying examination.
Top Exams Accepted by YMCA Faridabad
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