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ME VLSI and Embedded Systems at DY Patil College of Engineering, Pune Offline Course
Approved by AICTE
24 Months
Full timeQuick Facts
Exam GATE | Seats 9 |
Course Details
MODE
Full timeDURATION
24 MonthsMaster of Engineering (ME) in VLSI and Embedded Systems is a two-year full-time postgraduate program recognized by the All India Council for Technical Education (AICTE) and offered by the Savitribai Phule Pune University, Pune.
Important dates
| Exams and Events | Dates |
|---|
GATE Exam Date (Mode - Online) | 6 Feb'26 - 7 Feb'26 |
GATE Exam Date (Mode - Online) | 13 Feb'26 - 14 Feb'26 |
GATE Result Date (Mode - Online) | 18 Mar'26 - 18 Mar'26 |
Eligibility Criteria
Candidate should have passed/appeared Bachelor degree or equivalent in the relevant field of Engineering/Technology from State Governments/MHRD approved institutions, with at least 50 % Aggregate marks (at least 45% marks in case of candidates of backward class categories and persons with disability belonging to Maharashtra State only).
Admission Details
Having a Positive and valid GATE Score in the respective qualifying branch.
Top Exams Accepted by DY Patil College of Engineering, Pune
Know More About this College
Applications for Admissions are open.
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News and Notifications
May 02, 2026 :
MHT CET 2026 session 2 exam for PCM is scheduled to be conducted from May 12 to 21, 2026.
May 02, 2026 :
MHT CET 2026 results for session 1 is expected to be released in May 2026.
Apr 20, 2026 :
Apr 30, 2026