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M.Tech VLSI Design at Jyothishmathi Institute of Technology and Science, Karimnagar Offline Course
Approved by AICTE
24 Months
Full time
1,60,000Quick Facts
Total Fees 1.60 L | Exam GATE | Seats 18 |
Fees Details
General
₹ 1.60 L
Disclaimer: Data for total fees has been calculated based on all years/semesters as provided by the college. The actual fees may vary.
Course Details
MODE
Full timeDURATION
24 MonthsMaster of Technology (M.Tech) in VLSI Design is a two-year full-time postgraduate program recognized by the All India Council for Technical Education (AICTE) and offered by the Jawaharlal Nehru Technological University, Hyderabad.
Important dates
| Exams and Events | Dates |
|---|
GATE Application Date - Without late fee (Mode - Online) | 1 Sep'26 - 27 Sep'26 |
GATE Late Fee Application Date - With late fee (Mode - Online) | 4 Oct'26 - 4 Oct'26 |
GATE Application Correction Date (Mode - Online) | 13 Oct'26 - 20 Oct'26 |
GATE Choice of Exam City - City allotment (Mode - Online) | 3 Jan'27 - 3 Jan'27 |
GATE Exam Date (Mode - Online) | 5 Feb'27 - 6 Feb'27 |
GATE Exam Date (Mode - Online) | 12 Feb'27 - 13 Feb'27 |
GATE Exam Date (Mode - Online) | 19 Feb'27 - 20 Feb'27 |
GATE Result Date (Mode - Online) | 18 Mar'27 - 18 Mar'27 |
TS PGECET Counselling Date - Phase 2 & Final Phase: Reporting at concerned colleges for verification of original certificates along with tuition fee payment receipt (M.E./ M. Tech./ M. Arch) (Mode - Online) | 8 Sep'26 - 11 Sep'26 |
Eligibility Criteria
The candidate passed a Bachelor’s Degree or equivalent in the relevant field. Obtained at least 50% marks (45% marks in case of candidates belonging to the reserved category) in the qualifying Examination.
Admission Details
The candidate must pass the GATE or TS PGECET exam.
Top Exams Accepted by Jyothishmathi Institute of Technology and Science, Karimnagar
Know More About this College
Applications for Admissions are open.
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