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Quick Facts

Total Fees
2.00 L
Exam
GATE
Seats
18

Fees Details

General

2.00 L

Disclaimer: Data for total fees has been calculated based on all years/semesters as provided by the college. The actual fees may vary.

Course Details

MODE

Full time

DURATION

24 Months

Master of Engineering (ME) in Embedded Systems and VLSI Design a two-year full-time postgraduate program recognized by All India Council for Technical Education (AICTE) and offered by the Jawaharlal Nehru Technological University, Hyderabad.


Important dates

Exams and EventsDates
GATE
Application Date - Without late fee (Mode - Online)
27 Aug'25 - 28 Sep'25
GATE
Late Fee Application Date - With late fee (Mode - Online)
28 Sep'25 - 9 Oct'25
GATE
Score Card Date - Availability of Score Cards for download by paying a fee of Rs. 500 per test paper (Mode - Online)
31 May'25 - 30 Dec'25
GATE
Exam Date (Mode - Online)
6 Feb'26 - 7 Feb'26
GATE
Exam Date (Mode - Online)
13 Feb'26 - 14 Feb'26
GATE
Result Date (Mode - Online)
18 Mar'26 - 18 Mar'26

Eligibility Criteria

Bachelor's degree in Engg/Technology, AMIE/AMIETE or similar qualifications recognized by UGC as equivalent to B.E./B.Tech.

Admission Details

ADMISSION IN ME/MTECH THROUGH PGCET ’A’ CATEGORY 

1. The admissions for 70% of seats will be done by the Convener PGCET under the ‘A’ category as follows. 

2. The seats are to be filled by the Convener with the candidates who have qualified in GATE/TSPGCET and possessing 50% marks in aggregate in respect of other than SC/ST/BC and 45% marks in aggregate in respect of BC/ST/SC students.

ADMISSION IN ME/MTECH THROUGH PGCET ’B’ CATEGORY 

1. The admission for the remaining 30% seats will be done by the Management under the ‘B’ category on merit and as per the norms fixed by the TSCHE. 

2. After completing the admissions by the management the selection list will be forwarded to Telangana State Council for Higher Education for ratification before the cut-off date given by TSCHE.

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