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ME Embedded System and VLSI Design at CBIT Hyderabad Offline Course
Approved by AICTE
24 Months
Full time
3,03,200Quick Facts
Total Fees 3.03 L | Exam GATE | Seats 18 |
Fees Details
General
₹ 3.03 L
Disclaimer: Data for total fees has been calculated based on all years/semesters as provided by the college. The actual fees may vary.
Course Details
MODE
Full timeDURATION
24 MonthsMaster of Engineering (M.E.) in Embedded Systems and VLSI Design is a two-year full-time postgraduate Course offered by Chaitanya Bharathi Institute of Technology, Hyderabad recognized by All India Council for Technical Education (AICTE) and affiliated to Osmania University, Hyderabad.
Important dates
| Exams and Events | Dates |
|---|
GATE Exam Date (Mode - Online) | 6 Feb'26 - 7 Feb'26 |
GATE Exam Date (Mode - Online) | 13 Feb'26 - 14 Feb'26 |
GATE Result Date (Mode - Online) | 18 Mar'26 - 18 Mar'26 |
Eligibility Criteria
- A bachelors degree in Engg/Technology of Osmania University in the concerned discipline;
- AMIE/AMIETE or similar qualifications recognized by UPSC as equivalent to B.E./B.Tech.
- valid GATE Score obtained in the GATE Examination.
- Apart from requirements of qualifications as stated in the above, the admissions of sponsored candidates shall be taken.
- The number of Sponsored candidates shall not be more than two in each specialization and not more than five in each department.
- His/Her application shall be duly recommended by the sponsoring agency for admission to the course and forwarded to the Osmania University (Principal, University College of Engineering, Osmania University, Hyderabad
- These seats are considered as a supernumerary.
- He/She must be a permanent employee with the sponsoring agency for at least two years, after obtaining the qualifying degree.
- The sponsoring agency must be a Government establishment or a public-sector undertaking, or a reputed private undertaking.
- The sponsoring agency shall certify that the candidates will be granted leave for pursuing the M.E. Full-Time course.
- The candidates should satisfy the local/non-local status requirement as laid down in the AP Educational Institutions (Regulation of Admissions) Order as amended from time to time
Admission Details
Valid GATE Score obtained in the GATE Examination.
Top Exams Accepted by CBIT Hyderabad
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News and Notifications
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TS EAMCET 2026 exam registration process is expected to commence in March 2026.
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TS EAMCET 2026 exam for engineering is scheduled to be conducted from May 9 to 11, 2026.
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