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M.Tech VLSI and Embedded Systems at SJCET Palai Offline Course
Approved by AICTE
24 Months
Full timeQuick Facts
Exam GATE | Seats 9 |
Course Details
MODE
Full timeDURATION
24 MonthsMaster of Technology (M.Tech) in VLSI and Embedded Systems is a two-year full-time postgraduate program recognized by the All India Council for Technical Education (AICTE) and offered by the APJ Abdul Kalam Technological University, Thiruvananthapuram.
Important dates
| Exams and Events | Dates |
|---|
GATE Application Date - Without late fee (Mode - Online) | 27 Aug'25 - 28 Sep'25 |
GATE Late Fee Application Date - With late fee (Mode - Online) | 28 Sep'25 - 9 Oct'25 |
GATE Score Card Date - Availability of Score Cards for download by paying a fee of Rs. 500 per test paper (Mode - Online) | 31 May'25 - 30 Dec'25 |
GATE Exam Date (Mode - Online) | 6 Feb'26 - 7 Feb'26 |
GATE Exam Date (Mode - Online) | 13 Feb'26 - 14 Feb'26 |
GATE Result Date (Mode - Online) | 18 Mar'26 - 18 Mar'26 |
Eligibility Criteria
- Candidates must be citizens of India.
- The candidates should have studied the Graduate course in an institution approved by the AICTE/Deemed Universities. Candidates should have a minimum of 60% aggregate marks in the Engineering Degree examination.
- For SC/ST candidates a pass in the Engineering Degree course is sufficient. For SEBC students, a minimum of 54% aggregate marks in the Engineering Degree examination is mandatory.
- Candidates who have appeared for the final semester examination can also apply, provided he/she has passed all the subjects up to and including the 6th-semester exam (8th semester for B.Tech students). Selection of such candidates shall be subject to the production of a qualifying degree.
Admission Details
Candidates must have a valid GATE score.
Top Exams Accepted by SJCET Palai
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