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M.Tech VLSI Design at IGDTUW Delhi Offline Course
Approved by AICTE
24 Months
Full time
2,31,000Quick Facts
Total Fees 2.31 L | Exam GATE | Seats 30 |
Fees Details
General
₹ 2.31 L
Disclaimer: Data for total fees has been calculated based on all years/semesters as provided by the college. The actual fees may vary.
Course Details
MODE
Full timeDURATION
24 MonthsMaster of Technology (M.Tech) in Electronics and Communication Engineering (VLSI Design) is a two-year full-time postgraduate course and it is offered by Indira Gandhi Delhi Technical University for Women, Delhi, and approved by AICTE.
Relaxation in marks for reserved categories:
- Other Backward Class (OBC_NCL) / Defence Category (CW): 5% relaxation of marks in the minimum eligibility requirements.
- Scheduled Castes (SC) and Scheduled Tribes (ST) / Differently Abled Persons (PD):10% relaxation of marks in the minimum eligibility requirements.
- Kashmiri Migrant (KM): 10% relaxation of marks in the minimum eligibility requirements.
Eligibility Criteria
Minimum 60% or equivalent in the qualifying exam as under:
- B.Tech./B.E.Degree in Electronics & Communication Engineering /Electronics & Electrical Engineering / Electrical Engineering / Electronics & Instrumentation Engineering / Electronics & Telecommunication Engineering /Computer Science Engineering /Information Technology/Information Science Engineering or equivalent from a recognized University.
- AMIE/ AMIETE in relevant discipline.
- M.Sc.(Electronics/Physics with Electronics/ Informatics/ Computer Sciences).
Note: Candidate appearing in the Final year/semester of their qualifying degree may also apply.
Admission Details
The admission to M.Tech. the course will be on the basis of the valid GATE Score secured by applicants and thereafter on the basis of the marks secured in the qualifying examination, as per the eligibility. The first preference would be given to candidates having valid GATE scores.
Top Exams Accepted by IGDTUW Delhi
Student Reviews for M.Tech VLSI Design
4/5(1 Reviews)
College with decent placements and industry exposure
Posted on 29 Aug'16 by Anonymous
Batch of 2017-01-01 | M.Tech VLSI Design
This user chose to post anonymously
Batch of 2017-01-01 | M.Tech VLSI Design
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