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Memory Device Technology for AI ML Computing
Online
12 Weeks
Free Quick Facts
| Medium Of Instructions | Mode Of Learning | Mode Of Delivery |
|---|---|---|
| English | Self Study | Video and Text Based |
Courses and Certificate Fees
| Fees Informations | Certificate Availability | Certificate Providing Authority |
|---|---|---|
| INR 1000 | yes | IIT Hyderabad |
The Syllabus
- W1.0: Introductory video
- W1.1: Evolving Computing Paradigms
- W1.2: Von Neumann Architecture.
- W1.3: Memory Hierarchy and Classifications
- W1.4: Evolution of memory hierarchy with device technology
- W1.5: Classifications within memory hierarchy
- W2.1: Practical Implementation of Memory Hierarchy
- W2.2: Global Memory market Part 1
- W2.3: Global memory market part 2
- W2.4: Memory Array Architecture Part 1
- W2.5: Memory Array Architecture Part 2
- W3.1: Analog Memory Peripheral
- W3.2: Memory area efficiency and block level design
- W3.3: SRAM - introduction and cell structure
- W3.4: SRAM-Memory effect and HOLD operation
- W3.5: SRAM-Read operation
- W3.6: SRAM Read Operation Timing Diagram
- W4.1: SRAM Write operation
- W4.2: Noise margins
- W4.3: SRAM - Biasing, 8T SRAM and Scaling
- W4.4: DRAM Introduction and Memory Wall
- W4.5: DRAM Sub-system Architecture
- W5.1: 1T-1R DRAM Cell and leakage paths of a storage node
- W5.2: DRAM Refresh and Charge Sharing
- W5.3: DRAM Read Write Timing Diagrams
- W5.4: DRAM Scaling Challenges and Solutions
- W5.5: Intro to NAND Flash and Flash cell part-1
- W6.1: NAND Flash cell - Floating gate vs charge trap
- W6.2: Types of Flash Organisation , NAND Organisation
- W6.3: NAND Flash Program Operation
- W6.4: NAND Erase and Read Operations
- W6.5: Advancements in NAND Flash technology and ISPP
- W7.1: NAND Flash Reliability challenges, 3-D NAND
- W7.2: Review of Part-1 (Mod1-5)
- W7.3: eNVMs Fundamentals of two-terminal Memristors
- W7.4: eNVMs PCRAMs Fundamentals of Phase Change Memories
- W7.5: eNVMs PCRAMs Technology and commercialization
- W8.1: eNVMs RRAMs Fundamentals
- W8.2: eNVMs RRAMs VCRAM and CBRAM
- W8.3: eNVMs RRAMs - Performance Metrics & Commercialization
- W8.4: eNVMs MRAM spin GMR TMR
- W8.5: eNVM MRAMs Field and STT MRAM
- W9.1: eNVM MRAM SOT and Commercialization
- W9.2: Classification and development of AIML paradigm
- W9.3: AIML task and introduction to artificial neuron
- W9.4: Scaling up artificial neuron to ANN
- W9.5: ANNs backprop, inference and different architectures of neural networks
- W10.1: Convolution operations
- W10.2: Convolution neural networks
- W10.3: Computational and energy cost of AIML
- W10.4: Introduction to Neuromorphic Computing
- W10.5: Structure and Behaviour of the LIF Neuron
- W11.1: HW Implementation of LIF Neuron
- W11.2: Synaptic Plasticity and STDP
- W11.3: HW Implementation of Synaptic Plasticity
- W11.4: Intro to SNNs and Spike encoding
- W12.1: Supervised and Unsupervised Learning in SNNs
- W12.2: HW implementation of SNNs
- W12.3: Intro to In Memory Computing (IMC)
- W12.4: HW implementations of IMC
- W12.5: Conclusion and Future Trends