Search Colleges, Exams, Schools & more
Login
Digital VLSI Testing
Online
12 WeeksQuick Facts
| Medium Of Instructions | Mode Of Learning | Mode Of Delivery |
|---|---|---|
| English | Self Study | Video and Text Based |
Courses and Certificate Fees
| Fees Informations | Certificate Availability | Certificate Providing Authority |
|---|---|---|
| INR 1000 | yes | IIT Kharagpur |
The Syllabus
- Importance
- Challenges
- Levels of abstraction
- Fault Models
- Advanced issues
- Importance
- Challenges
- Levels of abstraction
- Fault Models
- Advanced issues
- Importance
- Challenges
- Levels of abstraction
- Fault Models
- Advanced issues
- Introduction
- Testability Analysis
- DFT Basics
- Scan cell design
- Scan Architecture
- Introduction
- Testability Analysis
- DFT Basics
- Scan cell design
- Scan Architecture
- Introduction
- Testability Analysis
- DFT Basics
- Scan cell design
- Scan Architecture
- Scan design rules
- Scan design flow
- Fault Simulation: Introduction, Simulation models
- Scan design rules
- Scan design flow
- Fault Simulation: Introduction, Simulation models
- Scan design rules
- Scan design flow
- Fault Simulation: Introduction, Simulation models
- Logic simulation
- Fault simulation
- Logic simulation
- Fault simulation
- Logic simulation
- Fault simulation
- Introduction
- Exhaustive testing
- Boolean difference
- Basic ATPG algorithms
- Introduction
- Exhaustive testing
- Boolean difference
- Basic ATPG algorithms
- Introduction
- Exhaustive testing
- Boolean difference
- Basic ATPG algorithms
- ATPG for non stuck-at faults
- Other issues in test generation Built-In-Self-Test: Introduction
- BIST design rules
- ATPG for non stuck-at faults
- Other issues in test generation Built-In-Self-Test: Introduction
- BIST design rules
- ATPG for non stuck-at faults
- Other issues in test generation Built-In-Self-Test: Introduction
- BIST design rules
- Test pattern generation
- Output response analysis
- Logic BIST architectures
- Test pattern generation
- Output response analysis
- Logic BIST architectures
- Test pattern generation
- Output response analysis
- Logic BIST architectures
- Introduction
- Stimulus compression
- Introduction
- Stimulus compression
- Introduction
- Stimulus compression
- Stimulus compression
- Response compression
- Stimulus compression
- Response compression
- Stimulus compression
- Response compression
- Introduction
- RAM fault models
- RAM test generation
- Introduction
- RAM fault models
- RAM test generation
- Introduction
- RAM fault models
- RAM test generation
- Memory BIST Power and Thermal Aware Test: Importance, Power models, Low power ATPG
- Memory BIST Power and Thermal Aware Test: Importance, Power models, Low power ATPG
- Memory BIST Power and Thermal Aware Test: Importance, Power models, Low power ATPG
- Low power BIST
- Thermal aware techniques
- Low power BIST
- Thermal aware techniques
- Low power BIST
- Thermal aware techniques